1. Field
This disclosure relates generally to a coherency managed processor system and, more specifically, to techniques for write-after-write ordering in a coherency managed processor system that employs an input/output command pipeline.
2. Related Art
While various architectures have memory models that are relaxed with respect to write ordering to different addresses, at least some architectures (e.g., the PowerPC™ architecture) require stronger ordering for input/output (I/O) operations. For example, in an I/O operation that involves updating one or more data blocks in a memory (e.g., a cache memory or a main memory) and then writing a control block (that is examined by a processor thread that is to receive the one or more data blocks) to indicate when the I/O operation is complete, the update of the one or more data blocks must complete before the control block update to maintain program integrity. In a sequential operation bus (i.e., in an architecture where only one operation occurs at a time), a control block cannot generally be updated before one or more associated data blocks are updated.
For example, in an architecture that employs a sequential operation bus, a master issues an initial write command, waits for confirmation of a completion of the initial write command, and then issues a next write command. However, in a conventional system that implements a coherent transport bus that is optimized for a weak ordering model (i.e., ordering is required only for accesses to a same address) with distributed coherency management, a stream of I/O commands with strong write-after-write ordering may not fully take advantage of the pipelined and distributed nature of the system. For example, a master cannot control a completion status of commands the master issues to a coherent transport bus. As such, if a command in a middle of a command stream fails, subsequent commands may complete and violate a desired completion order.